MC33596FCE/R2 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

MC33596FCE/R2

PLL Tuned UHF Receiver for Data Transfer Applications

NXP Semiconductors. 

Register Description

Table 9. Active Level of SWITCH Output Pin

SL

Receiver Function

Level on SWITCH

0

Receiving

—

1

—

Receiving

Low

High

Low

High

LVDE (Low Voltage Detection Enable) enables the low voltage detection function.

0 = disabled

1 = enabled

NOTE

This bit is cleared by POR. In the event of a complete loss of the supply

voltage, LVD is disabled at power-up, but the information is not lost as the

status bit LVDS is set by POR.

CLKE (Clock Enable) controls the DATACLK output buffer.

0 = DATACLK remains low

1 = DATACLK outputs Fdataclk

Figure 25 describes configuration register 2, CONFIG2.

Bit Name

Reset Value

Access

Bit 7

DSREF

0

R/W

Bit 6

FRM

0

R/W

Bit 5

Bit 4

Bit 3

Bit 2

MODU

DR1

DR0

TRXE

0

1

0

0

R/W

R/W

R/W

R/W

Figure 25. CONFIG2 Register

Bit 1

DME

0

R/W

Bit 0

SOE

0

R/W

Addr

$01

DSREF (Data Slicer Reference) selects the data slicer reference.

0 = Fixed reference (cannot be used in FSK)

1 = Adaptive reference (recommended for maximum sensitivity in OOK and FSK)

In the case of FSK modulation (MODU = 1), DSREF must be set.

FRM (Frequency Register Manager) enables either a user friendly access or a direct access to one

frequency register.

0 = The carrier frequency is defined by the F register

1 = The local oscillator frequency is defined by the F register.

MODU (Modulation) sets the data modulation type.

0 = On/Off Keying (OOK) modulation

1 = Frequency Shift Keying (FSK) modulation

DR[1:0] (Data Rate) configure the receiver blocks operating in base band.

• Low-pass data filter

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

35

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