CS5374 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5374

Dual High-performance Amplifier & ΔΣ Modulator

Cirrus Logic 

CS5374

DS862F1

CS5374

RST

Hardware

Configuration

SPI

Registers

Serial

Pin Logic

CS

SCLK

SDI

SDO

Figure 15. SPI Interface Block Diagram

5. SPITM SERIAL PORT

The CS5374 SPI interface is a slave serial port de-

signed to interface with the CS5376A SPI 2 port.

SPI commands from the CS5376A write and read

the CS5374 configuration registers to control hard-

ware operation.

A block diagram of the CS5374 SPI serial interface

is shown in Figure 15, and connections to the

CS5376A SPI 2 port are shown in Figure 12 on

page 15.

5.1 SPI Pin Descriptions

RST — Pin 37

Hardware reset input pin, active low. Defaults the

configuration registers and SPI state machine.

CS — Pin 25

Chip select input pin, active low.

SCLK — Pin 26

Serial clock input pin. Maximum 4.096 MHz.

SDI — Pin 27

Serial data input pin. Data expected valid on rising

edge of SCLK, transition on falling edge.

SDO — Pin 28

Serial data output pin. Data valid on rising edge of

SCLK, transition on falling edge.

5.2 SPI Serial Transactions

Following reset, master mode serial transactions to

CS5374 assert CS and write serial clocks to SCLK

while writing serial data into SDI or reading serial

data out from SDO.

The CS5374 serial port operates in SPI mode 0

(0,0) and reads or writes configuration registers us-

ing standard 8-bit SPI opcodes. Each individual se-

rial transaction is 24-bits long and is generated by

concatenating an 8-bit SPI command opcode, an 8-

bit register address, and an 8-bit data byte as shown

in Figure 16 on page 22.

The CS5374 SPI state machine requires 24 clocks

with CS asserted to fully shift out the SPI data or

else SPI clock synchronization can be lost. The

CS5376A SPI 2 hardware generates 24 clocks per

transaction and will keep the CS5374 serial port

synchronized at all times. However, if another SPI

master is used and clock synchronization is lost,

two methods are available to recover:

1. Hold CS high (inactive) and apply 24 clocks to

shift out any cached SPI data bits. This method re-

tains the existing CS5374 register configuration.

... or ...

2. Apply a hardware reset (toggle RST) and then

rewrite all CS5374 register configuration values.

DS862F1

21

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