Flash/EEPROM Memory
A/D Converter
AT89C51CC03
Table 128. Timing Symbol Definitions
Signals
S (Hardware
condition)
R
PSEN#,EA
RST
B
FBUSY flag
Conditions
L
Low
V
Valid
X
No Longer Valid
Table 129. Memory AC Timing
VDD = 3V to 5.5V, TA = -40 to +85°C
Symbol
TSVRL
TRLSX
TBHBL
NFCY
TFDR
Parameter
Input PSEN# Valid to RST Edge
Input PSEN# Hold after RST Edge
Flash/EEPROM Internal Busy
(Programming) Time
Number of Flash/EEPROM Erase/Write
Cycles
Flash/EEPROM Data Retention Time
Min
Typ
50
50
10
100 000
10
Figure 82. Flash Memory – ISP Waveforms
RST
PSEN#1
TSVRL
TRLSX
Max
Unit
ns
ns
ms
cycles
years
Figure 83. Flash Memory – Internal Busy Waveforms
FBUSY bit
TBHBL
Table 130. AC Parameters for A/D Conversion
Symbol
TSETUP
ADC Clock Frequency
Parameter
Min
Typ
Max
Unit
4
µs
700
KHz
4182K–CAN–05/06
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