M34D64-WMN6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

M34D64-WMN6

64 Kbit serial I²C bus EEPROM with hardware write control on top quarter of memory

STMicroelectronics 

Revision history

9

Revision history

M34D64-W

Table 14. Document revision history

Date

Revision

Changes

23-Mar-1999 1.0 Document written

09-Jun-1999

1.1 Memory Map illustration added. Line removed from Tab-2

16-Nov-2000

1.2

M34D32 removed; PSDIP8 package removed; 4.5 to 5.5V and 1.8 to

3.6V ranges removed; 0 to 70°C and -20 to 85°C ranges removed

13-Sep-2002 2.0 New edition. TSSOP8 package added

04-Apr-2003

Addresses on Memory Map figure corrected.

2.1 tW of 5ms offered on certain versions of the device (bearing process

identification letter “B”)

23-Oct-2007

M34D64-R root part number removed (R voltage range removed).

TSSOP8 package removed. SO8N packages are ECOPACK® compliant.

SO8N package specifications updated (sse Section 7: Package

mechanical data). Note removed below Table 9: Input parameters.

Table 6: Absolute maximum ratings and related notes modified.

3

Section 2: Signal description modified. Power On Reset: VCC Lock-Out

Write Protect section removed.

Rise/fall time conditions modified for ICC in Table 10: DC characteristics.

Write time tW updated in Table 11: AC characteristics.

Figure 11: AC waveforms modified. Minor text changes.

17-Apr-2008

Obsolete product(s) watermark removed.

4

Section 2.6.3: Device reset updated. Figure 5: Maximum RL value versus

bus capacitance (CBUS) for an I2C bus updated. Small text changes.

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