C8051F521-C-IM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F521-C-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

11.1. Power-On Reset

During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above

VRST. VDD ramp time is defined as how fast VDD ramps from 0 V to VRST. An additional delay (TPORDelay)

occurs before the device is released from reset. The VRST threshold and TPORDelay are specified in

Table 2.8, “Reset Electrical Characteristics,” on page 32. Figure 11.2 plots the power-on and VDD monitor

reset timing.

Note: Please refer to Section “20.4. VDD Monitors and VDD Ramp Time” on page 211 for definition of VRST and VDD

ramp time in older silicon revisions A and B.

On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is

set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other

resets). Since all resets cause program execution to begin at the same location (0x0000), software can

read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data

memory should be assumed to be undefined after a power-on reset. Both the VDD monitors (VDDMON0

and VDDMON1) are enabled following a power-on reset.

Note: Please refer to Section “11.2.1. VDD Monitor Thresholds and Minimum VDD” on page 108 for

recommendations related to minimum VDD.

VRST

VDD

1.0

t

/RST

Logic HIGH

Logic LOW

T PORDelay

P o w e r-O n

Reset

VDD

M onitor

Reset

Figure 11.2. Power-On and VDD Monitor Reset Timing

Rev. 1.4

107

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