CS5376
13.4.1 Interpolation Factor
The INTP bits select how many times the data in-
terpolation module will re-use a data point to gen-
erating the output bit stream. The value is zero
based and so represents one greater than the actual
register value. (0x0F => interpolation by 16).
13.4.2 Clock Rate
The RATE bits set the test bit stream generator in-
ternal clock rate. The output clock and data bit
stream rate from the TBSCLK and TBSDATA pins
are 1/8 of this frequency.
13.4.3 Clock Delay
The CDLY bits program a delay for TBSCLK, up
to 8 internal clock periods.
13.4.4 Loopback Enable
The LOOP bit enables the digital loopback connec-
tion into the digital filters.
13.4.5 Run Enable
The RUN bit enables the test bit stream generator.
13.4.6 Data Delay
The DDLY bits program a delay for TBSDATA,
up to 64 internal clock periods.
DS256PP1
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