
CS5376
9.3.3 OFFSET1 - OFFSET4 Registers
Figure 44. Offset Correction Register OFFSET1
(MSB) 23
OFST23
R/W
0
22
OFST22
R/W
0
21
OFST21
R/W
0
20
OFST20
R/W
0
19
OFST19
R/W
0
18
OFST18
R/W
0
17
OFST17
R/W
0
16
OFST16
R/W
0
15
OFST15
R/W
0
14
OFST14
R/W
0
13
OFST13
R/W
0
12
OFST12
R/W
0
11
OFST11
R/W
0
10
OFST10
R/W
0
9
OFST9
R/W
0
8
OFST8
R/W
0
7
OFST7
R/W
0
6
OFST6
R/W
0
5
OFST5
R/W
0
4
OFST4
R/W
0
3
OFST3
R/W
0
2
OFST2
R/W
0
1
OFST1
R/W
0
(LSB) 0
OFST0
R/W
0
I/O Address: 0x25
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable and
Writable
Bits in bottom rows
are reset condition
Bit definitions:
23:16 OFST[23:16] Offset Correction
Upper Byte
15:8 OFST[15:8] Offset Correction 15:8 OFST[7:0] Offset Correction
Middle Byte
Lower Byte
DS256PP1
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