CS5376 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

bit addresses generated when accessing an EE-

PROM in master mode.

5.1 SPI 1 Pin Descriptions

The Serial Peripheral Interface 1 port is a standard

3-wire, bidirectional, synchronous serial interface.

The SCK1, MISO, and MOSI pins, along with ei-

ther the CS11 or SSI chip select pins, are used to in-

terface the decimation engine of the CS5376 to

external serial devices. Several miscellaneous pins,

SINT, SSO, and CS8 - CS10 are not used but are

defined to make the SPI 1 port extensible in the fu-

ture.

CS11 - Pin 46

Master mode chip select output pin, active low. EE-

PROM chip select signal automatically generated

when booting in stand-alone mode.

SSI - Pin 49

Slave mode chip select input pin, active low. Chip

select signal that places the SPI 1 port into slave

mode to receive commands from a microcontroller.

SCK1 - Pin 48

Master mode serial clock output, slave mode serial

clock input. In both modes a serial clock rising

edge indicates valid data, a falling edge indicates a

data transition.

In master mode the SCK1 pin is an output that gen-

erates a serial clock to read data from the configu-

ration EEPROM. The serial clock output rate in

master mode defaults to 1.024 MHz.

In slave mode the SCK1 pin is an input that re-

ceives a serial clock from a microcontroller. The

serial clock input rate in slave mode can be any rate

up to a maximum of 4.096 MHz.

MOSI - Pin 51

Master Out, Slave In data pin. Data output in mas-

ter mode, data input in slave mode. Data is valid on

the rising edge of SCK1, and transitions on the fall-

ing edge.

MISO - Pin 50

Master In, Slave Out data pin. Data input in master

mode, data output in slave mode. Data is valid on

the rising edge of SCK1, and transitions on the fall-

ing edge.

SINT - Pin 52

SPI 1 interrupt output pin, active low. A pulsed

output indicates data was written to the SPI 1 reg-

isters by the decimation engine. Not used by

CS5376 rev A, reserved for future revisions.

SSO - Pin 47

Slave select output pin, active low. Chip select out-

put that mirrors the SSI pin. Not used by CS5376

rev A, reserved for future revisions.

CS8 - CS10 - Pins 43 - 46

Additional chip selects for SPI 1 master mode. Not

used by CS5376 rev A, reserved for future revi-

sions.

5.2 SPI 1 Stand-Alone Mode

In stand-alone mode, the SPI 1 port operates as an

SPI bus master to load configuration information

from an EEPROM. Commands to write configura-

tion registers, filter coefficients, and test bit stream

data are programmed into the EEPROM along with

the required data words.

The CS5376 automatically reads 1-byte command

and 3-byte data words from EEPROM memory un-

til the ‘Filter Start’ command is received. The ‘Fil-

ter Start’ command initializes the CS5376 digital

filters and places the SPI 1 port into slave mode.

See “SPI 1 Coprocessor Mode” on page 27 for

more information about SPI 1 slave mode.

DS256PP1

22

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