CS42438-DMZR View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS42438-DMZR

108 dB, 192 kHz 6-in, 8-out TDM CODEC

Cirrus Logic 

FS is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data

sample and must be held valid for at least 1 SCLK period.

NOTE: The ADC does not meet the timing requirements for proper operation in Quad-Speed

Mode.

FS

Bit or Word Wide

256 clks

SCLK

DAC_SDIN

ADC_SDOUT

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

AOUT1

AOUT2

AOUT3

AOUT4

AOUT5

AOUT6

AOUT7

AOUT8

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

LSB MSB

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AUX1

AUX2

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

Figure 14. TDM Serial Audio Format

5.5.2 I/O Channel Allocation

Digital

Input/Output

DAC_SDIN

ADC_SDOUT

Interface

Format

TDM

TDM

Analog Output/Input Channel Allocation

from/to Digital I/O

AOUT 1,2,3,4,5,6,7,8

AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN)

Table 6. Serial Audio Interface Channel Allocations

34

DS646PP2

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