CS42438-DMZR View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS42438-DMZR

108 dB, 192 kHz 6-in, 8-out TDM CODEC

Cirrus Logic 

SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE

(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF)

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

-

RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 20)

thdd

0

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

(Note 21)

trc

-

Fall Time SCL and SDA

(Note 21)

tfc

-

Setup Time for Stop Condition

tsusp

4.7

Acknowledge Delay from SCL Falling

tack

300

100

kHz

-

ns

-

µs

-

µs

-

µs

-

µs

-

µs

-

µs

-

ns

1

µs

300

ns

-

µs

1000

ns

Notes: 20. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

21. Guaranteed by design.

RST

t irs

Stop

Start

SDA

SCL

t buf

t hdst

t high

t

low

t

hdd

t sud t ack

Repeated

S ta rt

t rd

t hdst

Stop

t fd

t fc

t susp

t sust

t rc

Figure 7. Control Port Timing - I²C Format

DS646PP2

23

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