C511 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

MFG CO.

C511

8-Bit CMOS Microcontroller

Infineon Technologies 

C511 / C513

Notes: Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is

valid for the other cases accordingly.

In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the

falling edge of SLS (if transmitter is enabled).

In the case of master mode and CPHA = 0, the MSB becomes valid after the data has

been written into the shift register, i.e. at least one half SCLK clock cycle before the

first clock transition.

Figure 14

SSC Timing

Figure 15

External Clock Drive at XTAL1

Semiconductor Group

38

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