DSPIC33FJ32GS610-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

MFG CO.

DSPIC33FJ32GS610-I/PF

16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators

Microchip Technology 

TABLE 4-55: PORTG REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES

File

Name

SFR

Addr.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

TRISG 02F0

—

—

—

—

—

—

TRISG9 TRISG8 TRISG7 TRISG6

—

—

PORTG 02F2

—

—

—

—

—

—

RG9

RG8

RG7

RG6

—

—

LATG

02F4

—

—

—

—

—

—

LATG9 LATG8 LATG7 LATG6

—

—

ODCG 02F6

—

—

—

—

—

—

ODCG9 ODCG8 ODCG7 ODCG6

—

—

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 3

TRISG3

RG3

LATG3

ODCG3

Bit 2

TRISG2

RG2

LATG2

ODCG2

Bit 1

TRISG1

RG1

LATG1

ODCG1

Bit 0

All

Resets

TRISG0

RG0

LATG0

ODCG0

03CF

xxxx

0000

0000

TABLE 4-56: PORTG REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES

File

Name

SFR

Addr.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

TRISG 02F0

—

—

—

—

—

—

TRISG9 TRISG8 TRISG7 TRISG6

—

PORTG 02F2

—

—

—

—

—

—

RG9

RG8

RG7

RG6

—

LATG

02F4

—

—

—

—

—

—

LATG9 LATG8 LATG7 LATG6

—

ODCG 02F6

—

—

—

—

—

—

ODCG9 ODCG8 ODCG7 ODCG6

—

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

—

TRISG3

—

RG3

—

LATG3

—

ODCG3

Bit 2

TRISG2

RG2

LATG2

ODCG2

Bit 1

—

—

—

—

Bit 0

—

—

—

—

All

Resets

03CC

xxxx

0000

0000

TABLE 4-57: SYSTEM CONTROL REGISTER MAP

File Name

SFR

Addr.

Bit 15

Bit 14

Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

RCON

OSCCON

CLKDIV

PLLFBD

OSCTUN

REFOCON

ACLKCON

Legend:

Note 1:

2:

0740 TRAPR IOPUWR

—

—

—

—

— VREGS EXTR

SWR

0742

—

COSC<2:0>

—

NOSC<2:0>

CLKLOCK

—

0744

ROI

DOZE<2:0>

DOZEN

FRCDIV<2:0>

PLLPOST<1:0>

0746

—

—

—

—

—

—

—

0748

—

—

—

—

—

—

—

—

—

—

074E ROON

—

ROSSLP ROSEL

RODIV<3:0>

—

—

0750 ENAPLL APLLCK SELACLK —

—

APSTSCLR<2:0>

ASRCSEL FRCSEL

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

The RCON register Reset values are dependent on the type of Reset.

The OSCCON register Reset values are dependent on the FOSCx Configuration bits and on the type of Reset.

SWDTEN WDTO SLEEP

IDLE

LOCK

—

CF

—

—

PLLPRE<4:0>

PLLDIV<8:0>

TUN<5:0>

—

—

—

—

—

—

—

—

BOR

—

—

—

Bit 0

All

Resets

POR

OSWEN

—

—

xxxx(1)

0300(2)

0040

0030

0000

0000

2300

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