
TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED)
SFR Name
SFR
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 Bit 6 Bit 5
Bit 4
CORCON
MODCON
XMODSRT
XMODEND
YMODSRT
YMODEND
XBREV
DISICNT
Legend:
0044
—
—
—
US
EDT
DL<2:0>
SATA SATB SATDW
0046 XMODEN YMODEN
—
—
BWM<3:0>
YWM<3:0>
0048
XS<15:1>
004A
XE<15:1>
004C
YS<15:1>
004E
YE<15:1>
0050
BREN
XB<14:0>
0052
—
—
Disable Interrupts Counter Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ACCSAT
Bit 3
IPL3
Bit 2 Bit 1
PSV RND
XWM<3:0>
Bit 0
All
Resets
IF 0000
0000
0
xxxx
1
xxxx
0
xxxx
1
xxxx
xxxx
xxxx