
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 1-1:
DEVICE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Interrupt
Controller
23
23
23
8
16
PCU PCH PCL
Program Counter
Stack
Control
Logic
Loop
Control
Logic
Y Data Bus
X Data Bus
16
16
Data Latch
16
Data Latch
X RAM
Address
Latch
Y RAM
Address
Latch
16
16
Address Latch
Address Generator Units
DMA
RAM
PORTA
16
DMA
Controller
16
PORTB
16
PORTC
Program Memory
Data Latch
24
Instruction
Decode and
Control
Control Signals
to Various Blocks
OSC2/CLKO Timing
OSC1/CLKI Generation
FRC/LPRC
Oscillators
Voltage
Regulator
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
ROM Latch
EA MUX
16 16
Instruction Reg
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-Bit ALU
16
PORTD
PORTE
PORTF
PORTG
VCAP
VDD, VSS MCLR
Timers
1-5
UART1/2
ECAN1
ADC1
OC1-4
PWM
9x2
Analog
Comparator 1-4
IC1-4
QEI1,2
CNx
I2C1/2
SPI1,2
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
DS70591E-page 18
2009-2012 Microchip Technology Inc.