
SDRAM (Rev.1.31)
Single Data Rate
Apr. '02
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
Auto Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
/CS
tRP
/RAS
/CAS
tRFC
tRCD
/WE
CKE
DQM
A0-9,11
X
Y
A10
X
A12
X
BA0,1
DQ
0
0
D0 D0 D0 D0
PRE ALL REFA
ACT#0 WRITE#0
All banks must be idle before REFA is issued.
Italic parameter shows minimum case
MITSUBISHI ELECTRIC
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