CS5503-BP View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5503-BP

Non-aliasing, 16- & 20-bit A/D Converters

Cirrus Logic 

CS5501 CS5503

CS5501/CS5503

In such asynchronous configurations the CS5501

is operated much like a successive-approximation

converter with a Convert signal and a subsequent

read cycle.

If it is required to latch the 16-bit data, then 2

74HC595 8-bit "shift register with latch" parts

may be used instead of 74HC299’s.

Serial Interfaces

Figures A3 to A8 offer both the hardware and

software interfaces to several industry-standard

microcontrollers using the CS5501’s SEC and

AC output modes. In each instance a system in-

itialization routine is provided which configures

the controller’s I/O ports to accept the CS5501’s

serial data and clock outputs and/or generate its

own serial clock. The routine also sets the

CS5501 into a known state.

For each interface, a second subroutine is also

provided which will collect one complete 16-bit

output word from the CS5501. Figure A5 illus-

trates the detailed timing throughout the

subroutine for one particular interface - the

COPS family interface of Figure A4.

+5V +5V

+5V

CS5501

CS5503

SDATA

MODE

SCLK

CS

DRDY

A

S1

S2

QH

OE2

D0

PA D1

PB D2

PC D3

PD D4

PE D5

PF D6

PG D7

PH

OE1

OE2

A

S1

S2

OE1

PA

D8

PB D9

PC D10

PD D11

PE D12

PF D13

PG D14

PH D15

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DS31F54

Figure A2. 8-Bit Parallel Interface

CS

A0

SET

D

Q

INT

Q

RESET

Only needed for

interrupt driven systems

DRDY

(For polling)

35

Share Link: