CS5501 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5501 Datasheet PDF : 54 Pages
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CS5501 CS5503
CS5501/CS5503
APPENDIX A: APPLICATIONS
Parallel Interface
Figures A1 and A2 show two serial-to-parallel
conversion circuits for interfacing the CS5501 in
its SSC mode to 16- and 8-bit systems respec-
tively. Each circuit includes an optional
74HCT74 flip-flop to latch DRDY and generate
a level-sensitive interrupt.
Both circuits require that the parallel read process
be synchronized to the CS5501’s operation. That
is, the system must not try to enable the regis-
ters’ parallel output while they are accepting
serial data from the CS5501. The CS5501’s
DRDY falls just prior to serial data transmission
and returns high as the last bit shifts out. There-
fore, the DRDY pin can be polled for a rising
transition directly, or it can be latched as a level-
sensitive interrupt.
With the CS input tied low the CS5501 will shift
out every available sample (4kHz word rate with
a 4MHz master clock). Lower output rates (and
interrupt rates) can be generated by dividing
down the DRDY output and applying it to CS.
Totally asynchronous interfaces can be created
using a Shift Data control signal from the system
which enables the CS5501’s CS input and/or the
shift registers’ S1 inputs. The DRDY output can
then be used to disable serial data transmission
once an output word has been fully registered.
+5V +5V
+5V
CS5501
CS5503
SDATA
MODE
SCLK
CS
DRDY
A
PA
D0
PB
D1
PC
D2
S1
PD
D3
PE
D4
S2
PF
D5
QH
OE2
PG
OE1PH
D6
D7
A OE1 PA
D8
PB
D9
PC
D10
S1
PD
D11
PE
D12
S2
PF
D13
PG
D14
OE2 PH
D15
CS
SET
D
Q
INT
Q
RESET
Only needed for
interrupt driven systems
DRDY
(For polling)
Figure A1. 16-bit Parallel Interface
3344
DS31F54
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