CS2300-CP(2008) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS2300-CP Datasheet PDF : 32 Pages
| |||
CS2300-CP
8.5 Ratio (Address 06h - 09h)
7
MSB
MSB-8
LSB+15
LSB+7
6
5
4
3
2
1
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
0
MSB-7
MSB-15
LSB+8
LSB
These registers contain the User Defined Ratio as shown in the “Register Quick Reference” section on
page 23. These 4 registers form a single 32-bit ratio value as shown above. See “Output to Input Frequency
Ratio Configuration” on page 15 and “Calculating the User Defined Ratio” on page 29 for more details.
8.6 Function Configuration 1 (Address 16h)
7
ClkSkipEn
6
AuxLockCfg
5
Reserved
4
EnDevCfg3
3
Reserved
2
Reserved
1
Reserved
0
Reserved
8.6.1
8.6.2
Clock Skip Enable (ClkSkipEn)
This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the
CLK_IN has missing pulses.
ClkSkipEn
0
1
Application:
PLL Clock Skipping Mode
Disabled.
Enabled.
“CLK_IN Skipping Mode” on page 13
Note: fCLK_IN must be < 80 kHz to use this feature.
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
AuxLockCfg
0
1
Application:
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 19
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
8.6.3
Enable Device Configuration Registers 3 (EnDevCfg3)
This bit, in conjunction with EnDevCfg1 and EnDevCfg2, enables control port mode. All three bits must
be set to 1 during initialization.
EnDevCfg3
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 21
Note: EnDevCfg1 and EnDevCfg2 must also be set to enable control port mode (“SPI / I²C Control Port”
on page 21).
DS843PP1
27
Share Link: 