JS48F4400P0VB00 View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

MFG CO.

JS48F4400P0VB00

Numonyx™ StrataFlash® Embedded Memory (P30)

Numonyx -> Micron 

P30

Table 24: Command Codes and Definitions (Sheet 2 of 2)

Mode

Code

Device Mode

Description

Block Locking/

Unlocking

Protection

Configuration

0x60

0x01

0xD0

0x2F

0xC0

0x60

0x03

Lock Block Setup

Lock Block

Unlock Block

Lock-Down Block

Program Protection

Register Setup

Read Configuration

Register Setup

Read Configuration

Register

First cycle of a 2-cycle command; prepares the CUI for block lock

configuration changes. If the next command is not Block Lock (0x01), Block

Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register bits

SR[4] and SR[5], indicating a command sequence error.

If the previous command was Block Lock Setup (0x60), the addressed block

is locked.

If the previous command was Block Lock Setup (0x60), the addressed block

is unlocked. If the addressed block is in a lock-down state, the operation has

no effect.

If the previous command was Block Lock Setup (0x60), the addressed block

is locked down.

First cycle of a 2-cycle command; prepares the device for a Protection

Register or Lock Register program operation. The second cycle latches the

register address and data, and starts the programming algorithm

First cycle of a 2-cycle command; prepares the CUI for device read

configuration. If the Set Read Configuration Register command (0x03) is not

the next command, the CUI sets Status Register bits SR[4] and SR[5],

indicating a command sequence error.

If the previous command was Read Configuration Register Setup (0x60), the

CUI latches the address and writes A[15:0] to the Read Configuration

Register. Following a Configure Read Configuration Register command,

subsequent read operations access array data.

November 2007

Order Number: 306666-11

Datasheet

47

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