ST72F324K2TATX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72F324K2TATX

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

set and IC2R can be loaded) but the user must take care that the counter is reset each

period and ICF1 can also generate an interrupt if ICIE is set.

5 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

6 In Flash devices, the TAOC2HR, TAOC2LR registers in Timer A are “write only”. A read

operation returns an undefined value.

7 In Flash devices, the ICAP2 registers (TAIC2HR, TAIC2LR) are not available in Timer A. The

ICF2 bit is forced by hardware to 0.

10.3.4 Low power modes

Table 46. Effect of low power modes on 16-bit timer

) Mode

Description

ct(s Wait

No effect on 16-bit timer.

Timer interrupts cause the device to exit from Wait mode.

du 16-bit timer registers are frozen.

ro In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes

P from the previous count when the MCU is woken up by an interrupt with ‘Exit from Halt

te Halt mode’ capability or from the counter reset value when the MCU is woken up by a reset.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is

le armed. Consequently, when the MCU is woken up by an interrupt with ‘Exit from Halt

o mode’ capability, the ICFi bit is set, and the counter value present when exiting from Halt

bs mode is captured into the ICiR register.

Obsolete Product(s) - O 10.3.5

Interrupts

Table 47. 16-bit timer interrupt control/wake-up capability

Interrupt event(1)

Event flag Enable Control bit Exit from WAIT Exit from HALT

Input Capture 1 event/counter

reset in PWM mode

ICF1

ICIE

Input Capture 2 event

ICF2(2)

Output Compare 1 event

(not available in PWM mode)

OCF1

Yes

No

OCIE

Output Compare 2 event

(not available in PWM mode)

OCF2(2)

Timer Overflow event

TOF

TOIE

1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 7: Interrupts).

These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

2. In Flash devices, the ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no

interrupt event for these flags.

Doc ID 13841 Rev 1

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