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ST72F324K2TCTR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
ST72F324K2TCTR Datasheet PDF : 194 Pages
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Interrupts
ST72324xx-Auto
Figure 19. Nested interrupt management
Software
priority
I1
I0
level
TRAP
3
11
IT0
3
11
IT1
IT1
2
00
IT2
IT2
1
01
IT3
RIM
IT4
IT4
3
11
3
11
Main
11 / 10
Main
3/0
10
uct(s) 7.5
Obsolete Product(s) - Obsolete Prod 7.5.1
Interrupt registers
CPU CC register interrupt bits
CPU CC
7
1
R/ W
6
1
R/ W
5
I1
R/ W
4
H
R/ W
3
I0
R/ W
Reset value: 111x 1010(xAh)
2
1
0
N
Z
C
R/ W
R/ W
R/ W
Table 15. CPU CC register interrupt bits description
Bit Name
Function
5 I1 Software Interrupt Priority 1
3 I0 Software Interrupt Priority 0
Table 16. Interrupt software priority levels
Interrupt software priority
Level
I1
I0
Level 0 (main)
Low
1
0
Level 1
0
1
Level 2
Level 3 (= interrupt disable)(1)
0
0
High
1
1
1. TRAP and RESET events can interrupt a level 3 program.
These two bits indicate the current interrupt software priority (see Table 16) and are
set/cleared by hardware when entering in interrupt. The loaded value is given by the
corresponding bits in the interrupt software priority registers (ISPRx).
46/193
Doc ID 13841 Rev 1

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