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ST72F324K6TC View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
ST72F324K6TC Datasheet PDF : 194 Pages
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ST72324xx-Auto
Figure 13. RESET sequences
VDD
VIT+(LVD)
VIT-(LVD)
Run
LVD
reset
Active phase
Supply, reset and clock management
External
reset
Run
Active
phase
Watchdog
reset
Run Active
phase
Run
t(s) External
c RESET
source
rodu RESET pin
P Watchdog
solete reset
th(RSTL)in
tw(RSTL)out
Watchdog underflow
Internal reset (256 or 4096 TCPU)
Vector fetch
) - Ob 6.5
Obsolete Product(s 6.5.1
System integrity management (SI)
The system integrity management block contains the LVD and auxiliary voltage detector
(AVD) functions. It is managed by the SICSR register.
LVD (low voltage detector)
The LVD function generates a static reset when the VDD supply voltage is below a VIT-
reference value. This means that it secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-
on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when VDD is below:
– VIT+ when VDD is rising
– VIT- when VDD is falling
The LVD function is illustrated in Figure 13.
The voltage threshold can be configured by option byte to be low, medium or high.
Doc ID 13841 Rev 1
37/193

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