ST72F324J2TCTX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72F324J2TCTX

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

Electrical characteristics

Figure 84. SPI master timing diagram(1)

SS INPUT

tc(SCK)

CPHA = 0

CPOL = 0

CPHA = 0

CPOL = 1

CPHA = 1

CPOL = 0

CPHA = 1

CPOL = 1

duct(s) MISO INPUT

tsu(MI)

th(MI)

tw(SCKH)

tw(SCKL)

MSB IN

tv(MO)

BIT6 IN

Pro MOSI OUTPUT See note 2

MSB OUT

BIT6 OUT

tr(SCK)

tf(SCK)

th(MO)

LSB IN

LSB OUT

See note 2

lete 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

so 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its

b alternate function capability released. In this case, the pin status depends on the I/O port configuration.

) - O 12.13 10-bit ADC characteristics

t(s Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

uc Table 110. 10-bit ADC characteristics

rod Symbol

Parameter

Conditions

Min Typ

P fADC

te VAREF

ole VAIN

ADC clock frequency

Analog reference voltage

Conversion voltage range(1)

ObsIlkg

Positive input leakage current for

analog input(2)

0.7*VDD < VAREF < VDD

-40°C < TA < +85°C

+85°C < TA < +125°C

0.4

3.8

VSSA

Max

2

VDD

VAREF

±250

±1

Unit

MHz

V

nA

µA

RAIN

CAIN

fAIN

External input impedance

External capacitor on analog input

Variation freq. of analog input signal

See

kΩ

figures

85 and

pF

86

Hz

CADC

tADC

Internal sample and hold capacitor

Conversion time (Sample + Hold)

fCPU = 8 MHz, Speed = 0,

fADC = 2 MHz

No. of sample capacitor loading cycles

No. of Hold conversion cycles

12

pF

7.5

µs

4

11

1/fADC

Doc ID 13841 Rev 1

171/193

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