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ST72F324J2TATRS View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
ST72F324J2TATRS Datasheet PDF : 194 Pages
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Electrical characteristics
ST72324xx-Auto
12.6
12.6.1
Clock and timing characteristics
Subject to general operating conditions for VDD, fCPU, and TA.
General timings
Table 92. General timings
Symbol
Parameter
Conditions Min Typ(1) Max Unit
tc(INST) Instruction cycle time
2
fCPU = 8 MHz 250
3
12 tCPU
375 1500 ns
Obsolete Product(s) - Obsolete Product(s) 12.6.2
tv(IT)
10
Interrupt reaction time tv(IT) = Δtc(INST) + 10(2)
fCPU = 8 MHz 1.25
22 tCPU
2.75 µs
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
External clock source
Table 93. External clock source
Symbol
Parameter
Conditions Min Typ Max Unit
VOSC1H OSC1 input pin high level voltage
VOSC1L OSC1 input pin low level voltage
VDD-1
VSS
VDD
V
VSS+1
tw(OSC1H)
tw(OSC1L)
OSC1 high or low time(1)
tr(OSC1)
tf(OSC1)
OSC1 rise or fall time(1)
See Figure 67.
5
ns
15
Ilkg OSC1 input leakage current
VSS < VIN < VDD
±1 µA
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 67. Typical application with an external clock source
VOSC1H
90%
10%
VOSC1L
tr(OSC1)
tf(OSC1)
tw(OSC1H)
tw(OSC1L)
External
clock source
OSC2
OSC1
Not connected internally
fOSC
Ilkg
ST72XXX
154/193
Doc ID 13841 Rev 1

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