ST72F324J4TCRS View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72F324J4TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

Table 57. SPICSR register description (continued)

Bit Name

Function

Mode Fault flag

4 MODF

This bit is set by hardware when the SS pin is pulled low in master mode (see

Master mode fault (MODF) on page 104). An SPI interrupt can be generated if

SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An

access to the SPICR register while MODF = 1 followed by a write to the SPICR

register).

0: No master mode fault detected

1: A fault in master mode has been detected.

3

- Reserved, must be kept cleared.

SPI Output Disable

ct(s) 2 SOD

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI output (MOSI in master mode / MISO in slave mode).

0: SPI output enabled (if SPE = 1).

1: SPI output disabled.

du SS Management

olete Pro 1 SSM

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI SS pin and uses the SSI bit value instead. See Slave Select management

on page 100.

0: Hardware management (SS managed by external pin).

1: Software management (internal SS signal controlled by SSI bit. External SS pin

free for general-purpose I/O).

bs SS Internal mode

t(s) - O 0 SSI

This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the

level of the SS slave select signal when the SSM bit is set.

0: Slave selected.

1: Slave deselected.

duc SPI Data I/O Register (SPIDR)

Pro SPIDR

Reset value: undefined

te7

6

5

4

3

2

1

0

le D7

D6

D5

D4

D3

D2

D1

D0

Obso R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

The SPIDR register is used to transmit and receive data on the serial bus. In a master

device, a write to this register will initiate transmission/reception of another byte.

Note:

During the last clock cycle the SPIF bit is set and a copy of the received data byte in the shift

register is moved to a buffer. When the user reads the serial peripheral data I/O register, the

buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

register is read.

Doc ID 13841 Rev 1

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