
PLDS
PSD8XXFX
Table 15. DPLD and CPLD inputs (continued)
Input source
Input name
Number of
signals
Page register
PGR7-PGR0
8
Macrocell AB feedback
MCELLAB.FB7-FB0
8
Macrocell BC feedback
MCELLBC.FB7-FB0
8
Secondary Flash memory Program Status
Bit
Ready/Busy
1
1. The address inputs are A19-A4 in 80C51XA mode.
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Doc ID 7833 Rev 7