
PSD8XXFX
AC/DC parameters
Figure 41. Asynchronous Reset / Preset
tARPW
RESET/PRESET
INPUT
REGISTER
OUTPUT
tARP
AI02864
Figure 42. Asynchronous Clock mode Timing (product term clock)
t(s) CLOCK
duc INPUT
Pro REGISTERED
lete OUTPUT
tCHA
tCLA
tSA tHA
tCOA
AI02859
bso Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices)
t(s) - O Symbol Parameter
Conditions
-70
-90
Min Max Min Max
-15
Min Max
PT Turbo Slew
Aloc off rate
Unit
Obsolete Produc fMAXA
Maximum
frequency
External
feedback
Maximum
frequency
Internal
feedback
(fCNTA)
Maximum
1/(tSA+tCOA)
1/(tSA+tCOA–10)
38.4
62.5
26.32
35.71
21.27
27.78
MHz
MHz
frequency
1/(tCHA+tCLA)
71.4
41.67
35.71
MHz
Pipelined data
tSA
Input setup
time
7
8
12
+ 2 + 10
ns
tHA
Input hold
time
8
12
14
ns
tCHA
Clock input
high time
9
12
15
+ 10
ns
tCLA
Clock input
low time
9
12
15
+ 10
ns
Doc ID 7833 Rev 7
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