SI5332C-C-GM3R View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

SI5332C-C-GM3R

6/8/12-Output Any-Frequency Clock Generator

Silicon Laboratories 

3.5.2 Differential Output Terminations

Si5332 Data Sheet

Functional Description

LVDS Driver Termination

For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 Ω and 132 Ω. The actual

value should be selected to match the differential impedance (Z0) of the transmission line. A typical point-to-point LVDS design uses a

100 Ω parallel resistor at the receiver and a 100 Ω differential transmission-line environment. In order to avoid any transmission-line

reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. The standard

LVDS termination schematic as shown in Figure 3.5 Standard LVDS Termination on page 12 can be used with either type of output

structure. Figure 3.6 Optional LVDS Termination on page 12, which can also be used with both output types, is an optional termina-

tion with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50 pF. If using a non-

standard termination, please contact Silicon Labs to confirm if the output structure is current source or voltage source type. In addition,

since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compati-

bility with the output.

LVDS

Driver

Zo = ZT/2

Zo = ZT/2

+

ZT

LVDS

Receiver

-

Figure 3.5. Standard LVDS Termination

LVDS

Driver

Zo = ZT/2

Zo = ZT/2

+

ZT/2 LVDS

C

ZT/2

Receiver

-

Figure 3.6. Optional LVDS Termination

Termination for 3.3 V LVPECL Outputs

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom-

mended only as guidelines. The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC

current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines.

Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 3.7 3.3 V

LVPECL Output Termination, Option 1 on page 13 and Figure 3.8 3.3 V LVPECL Output Termination, Option 2 on page 13 show

two different layouts. Other suitable clock layouts may exist, and it would be recommended that the board designers simulate to guar-

antee compatibility across all printed circuit and clock component process variations.

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