M38862ECAFS View Datasheet(PDF) - Renesas Electronics
Part Name
Description
MFG CO.
M38862ECAFS Datasheet PDF : 111 Pages
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MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 42 Switching characteristics 1
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test
conditions
Limits
Unit
Min.
Typ. Max.
tWH (SCLK1)
Serial I/O1 clock output “H” pulse width
tC(SCLK1)/2–30
ns
tWL (SCLK1)
Serial I/O1 clock output “L” pulse width
tC(SCLK1)/2–30
ns
td (SCLK1-TXD)
tV (SCLK1-TXD)
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Fig. 83
–30
140
ns
ns
tr (SCLK1)
Serial I/O1 clock output rising time
30
ns
tf (SCLK1)
Serial I/O1 clock output falling time
30
ns
tWH (SCLK2)
Serial I/O2 clock output “H” pulse width
tC(SCLK2)/2–160
ns
tWL (SCLK2)
Serial I/O2 clock output “L” pulse width
tC(SCLK2)/2–160
ns
td (SCLK2-SOUT2) Serial I/O2 output delay time
tV (SCLK2-SOUT2) Serial I/O2 output valid time
Fig. 84
0
200
ns
ns
tf (SCLK2)
Serial I/O2 clock output falling time
30
ns
tr (CMOS)
tf (CMOS)
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Fig. 83
10 30
ns
10 30
ns
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
Table 43 Switching characteristics 2
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test
conditions
Limits
Unit
Min.
Typ. Max.
tWH (SCLK1)
Serial I/O1 clock output “H” pulse width
tC(SCLK1)/2–50
ns
tWL (SCLK1)
Serial I/O1 clock output “L” pulse width
tC(SCLK1)/2–50
ns
td (SCLK1-TXD)
tV (SCLK1-TXD)
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Fig. 83
–30
350
ns
ns
tr (SCLK1)
Serial I/O1 clock output rising time
50
ns
tf (SCLK1)
Serial I/O1 clock output falling time
50
ns
tWH (SCLK2)
Serial I/O2 clock output “H” pulse width
tC(SCLK2)/2–240
ns
tWL (SCLK2)
Serial I/O2 clock output “L” pulse width
tC(SCLK2)/2–240
ns
td (SCLK2-SOUT2) Serial I/O2 output delay time
Fig. 84
400
ns
tV (SCLK2-SOUT2) Serial I/O2 output valid time
0
ns
tf (SCLK2)
Serial I/O2 clock output falling time
50
ns
tr (CMOS)
tf (CMOS)
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
Fig. 83
20 50
ns
20 50
ns
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
97
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