S25FL128SAGNFVQ00 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
S25FL128SAGNFVQ00
Cypress Semiconductor
S25FL128SAGNFVQ00 Datasheet PDF : 144 Pages
| |||
S25FL128S, S25FL256S
Then the memory contents, at the address given, is shifted out, in DDR fashion, one bit at a time on each clock edge through SO.
Each bit is shifted out at the SCK frequency by the rising and falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
The EHPLC table does provide cycles for mode bits so a series of DDR Fast Read commands may eliminate the 8 bit instruction
after the first DDR Fast Read command sends a mode bit pattern of complementary first and second Nibbles, e.g. A5h, 5Ah, 0Fh,
etc., that indicates the following command will also be a DDR Fast Read command. The first DDR Fast Read command in a series
starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits, followed by a latency period. If the mode
bit pattern is complementary the next command is assumed to be an additional DDR Fast Read command that does not provide
instruction bits. That command starts with address, followed by mode bits, followed by latency.
When the EHPLC table is used, address jumps can be done without the need for additional DDR Fast Read instructions. This is
controlled through the setting of the Mode bits (after the address sequence, as shown in Figure 9.41 on page 92 and Figure 9.43
on page 93. This added feature removes the need for the eight bit SDR instruction sequence to reduce initial access time (improves
XIP performance). The Mode bits control the length of the next DDR Fast Read operation through the inclusion or exclusion of the
first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah)
then the next address can be entered (after CS# is raised high and then asserted low) without requiring the 0Dh or 0Eh instruction,
as shown in Figure 9.42 and Figure 9.44, thus, eliminating eight cycles from the command sequence. The following sequences will
release the device from this continuous DDR Fast Read mode; after which, the device can accept standard SPI commands:
1. During the DDR Fast Read Command Sequence, if the Mode bits are not complementary the next time CS# is raised high
the device will be released from the continuous DDR Fast Read mode.
2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (SI) are not set for a valid
instruction sequence, then the device will be released from DDR Fast Read mode.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
The HOLD function is not valid during any part of a Fast DDR Command.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h
(or 00110100) will be driven on each of the active outputs (i.e. all four IOs on a x4 device, both IOs on a x2 device and the single SO
output on a x1 device). This pattern was chosen to cover both DC and AC data transition scenarios. The two DC transition scenarios
include data low for a long period of time (two half clocks) followed by a high going transition (001) and the complementary low going
transition (110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by a high going
transition (101) and the complementary low going transition (010). The DC transitions will typically occur with a starting point closer
to the supply rail than the AC transitions that may not have fully settled to their steady state (DC) levels. In many cases the DC
transitions will bound the beginning of the data valid period and the AC transitions will bound the ending of the data valid period.
These transitions will allow the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been
characterized the optimal data capture point can be chosen. See Section 7.5.11, SPI DDR Data Learning Registers on page 55 for
more details.
Figure 9.41 DDR Fast Read Initial Access (3-byte Address, 0Dh [ExtAdd=0, EHPLC=11b])
CS#
SCK
IO0
IO1
0
1
2
3
4
5
6
7
8
19
20
21
22
23
24
25
26
27
28
29
8 cycles
Instruction
12 cycles
24 Bit Address
4 cycles
Mode
1 cyc
Dummy
7
6
5
4
3
2
1
0 221076543210
4 cycles
per data
7 654321076
Document Number: 001-98283 Rev. *I
Page 92 of 144
Share Link: 