ST7263
I/O PORTS (Cont’d)
Table 10. PA1, PA2 Description
PORT A
PA1
PA2
*Reset State
Input*
without pull-up
without pull-up
I/O
Output
Very High Current open drain
Very High Current open drain
Figure 19. PA1, PA2 Configuration
ALTERNATE ENABLE
ALTERNATE 1
OUTPUT
0
DR
LATCH
Alternate Function
Signal
Condition
SDA (I2C data)
I2C enable
SCL (I2C clock)
I2C enable
DDR
LATCH
PAD
DDR SEL
DR SEL
1
0
N-BUFFER
ALTERNATE ENABLE
VSS
CMOS SCHMITT TRIGGER
28/109