Electrical characteristics
STM32F301x6 STM32F301x8
6.3.19 DAC electrical specifications
Symbol
Table 68. DAC characteristics
Parameter
Conditions
Min
VDDA
RLOAD(1)
RO(1)
CLOAD(1)
Analog supply voltage
Resistive load
Output impedance
Capacitive load
VDAC_OUT (1)
Voltage on DAC_OUT
output
DAC output buffer ON
2.4
DAC output buffer ON
5
DAC output buffer ON
-
DAC output buffer ON
-
Corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VDDA = 3.6 V
and (0x155) and (0xEAB) at
0.2
VDDA = 2.4 V DAC output
buffer ON.
DAC output buffer OFF
-
DAC DC current
With no load, middle code
(0x800) on the input.
-
IDDA(3)
consumption in quiescent
mode (Standby mode)(2)
With no load, worst code
(0xF1C) on the input.
-
DNL(3)
Differential non linearity
Difference between two
consecutive code-1LSB)
Given for a 10-bit input code -
Given for a 12-bit input code -
INL(3)
Integral non linearity
Given for a 10-bit input code -
(difference between
measured value at Code i
and the value at Code i on a Given for a 12-bit input code -
line drawn between Code 0
and last Code 4095)
-
-
Offset(3)
Offset error (difference
between measured value at
Code (0x800) and the ideal
Given for a 10-bit input code
at VDDA = 3.6 V
-
value = VDDA/2)
Given for a 12-bit input code
at VDDA = 3.6 V
-
Gain error(3) Gain error
Given for a 12-bit input code -
Settling time (full scale: for a
12-bit input code transition
tSETTLING(3)
between the lowest and the CLOAD 50 pF,
highest input codes when RLOAD 5 k
-
DAC_OUT reaches final
value ±1LSB
Max frequency for a correct
Update rate(3)
DAC_OUT change when
small variation in the input
CLOAD 50 pF,
RLOAD 5 k
-
code (from code i to i+1LSB)
Typ
Max
Unit
-
3.6
V
-
-
k
-
15
k
-
50
pF
-
VDDA – 0.2
V
0.5 VDDA - 1LSB mV
-
380
μA
-
480
μA
-
±0.5
LSB
-
±2
LSB
-
±1
LSB
-
±4
LSB
-
±10
mV
-
±3
LSB
-
±12
LSB
-
±0.5
%
3
4
μs
-
1
MS/s
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