QL8250-7PS484M(2002) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL8250-7PS484M
(Rev.:2002)

Low Power FPGA Combining Performance, Density, and Embeded RAM

QuickLogic Corporation 

(FOLSVH,, )DPLO\ 'DWD 6KHHW 5HY %

CLK

D

tSU

tHL

Q

tCO

)LJXUH  /RJLF &HOO )OLS)ORS 7LPLQJV²6HFRQG :DYHIRUP

&ORFN 6RXUFH

Logic Cells (Internal)

Clock Pad

7DEOH  (FOLSVH,, &ORFN 'HOD\

3DUDPHWHUV

&ORFN 3HUIRUPDQFH

*OREDO

'HGLFDWHG

Clock signal generated internally 1.51 ns (max)

-

Clock signal generated externally 2.06 ns (max)

1.73 ns

&ORFN 6HJPHQW

tPGCK

tBGCK

7DEOH  (FOLSVH,, *OREDO &ORFN 'HOD\

3DUDPHWHU

0LQ

Global clock pin delay to quad net

-

Global clock tree delay

(quad net to flip-flop)

-

9DOXH

0D[

1.34 ns

0.56 ns

NOTE: :KHQ XVLQJ D 3// W3*&. DQG W%*&. DUH HIIHFWLYHO\ ]HUR GXH WR GHOD\ DGMXVWPHQW E\

3KDVH /RFNHG /RRS



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