QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5632
(Rev.:2003)
(Rev.:2003)
QuickLogic Corporation
QL5632 Datasheet PDF : 39 Pages
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QL5632 Enhanced QuickPCI Device Data Sheet Rev. C
Signal
Cfg_SERR_Sig
Cfg_MstPERR_Det
Usr_TRDY
Usr_STOPO
Usr_DEVSEL
Usr_Last_Cycle_D1
Usr_Rdy
Usr_Stop
Usr_Abort
Table 11: PCI Target Interface (Continued)
Type
Description
System error asserted on the PCI bus. When this signal is active, the
O Signalled System Error bit, bit 14 of the Status Register, must be set in
the PCI configuration space (offset 04h).
Data parity error detected on the PCI bus by the master. When this signal
O is active, bit 8 of the Status Register must be set in the PCI configuration
space (offset 04h).
O
Inverted copy of the TRDYN signal as driven by the PCI target interface.
Valid only within a target access.
O
Inverted copy of the STOPN signal as driven by the PCI target interface.
Valid only within a target access.
O
Inverted copy of the DEVSELN signal as driven by the PCI target
interface. Valid only within a target access.
O
Active one clock cycle after the last data phase (may not with data
transfer) occurs on PCI and inactive one clock cycle afterwards.
Used to delay (add wait states to) a target PCI transaction when the
I backend needs additional time to provide data (read) or accept data
(write). Subject to PCI latency restrictions.
I Used to prematurely stop a PCI target access on the next PCI clock.
I
Used to signal Target Abort on PCI when the backend has fatal error and
is unable to complete a transaction. Rarely used.
PCI Internal Signals
Signal
PCI_clock
PCI_reset
PCI_IRDYN_D1
PCI_FRAMEN_D1
PCI_DEVSELN_D1
PCI_TRDYN_D1
PCI_STOPN_D1
PCI_IDSEL_D1
Type
O
O
O
O
O
O
O
O
Table 12: PCI Internal Signal
Description
PCI clock.
PCI reset signal.
Copy of the IRDYN signal from the PCI bus, delayed by one clock.
Copy of the FRAMEN signal from the PCI bus, delayed by one clock.
Copy of the DEVSELN signal from the PCI bus, delayed by one clock.
Copy of the TRDYN signal from the PCI bus, delayed by one clock.
Copy of the STOPN signal from the PCI bus, delayed by one clock.
Copy of the IDSEL signal from the PCI bus, delayed by one clock.
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