CS5501-AS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5501-AS

Low-Cost, 16 & 20-Bit Measurement A/D Converter

Cirrus Logic 

CS5501/CS5503

The recommended system connection diagram for

the CS5501/CS5503 is illustrated in Figure 15.

Note that any digital logic inputs which are to be

unused should be tied to either DGND or the

VD+ as appropriate. They should not be left float-

ing; nor should they be tied to some other logic

supply voltage in the system.

Power-Up and Initialization

Upon power-up, a calibration cycle must be initi-

ated at the CAL pin to insure a consistent starting

condition and to initially calibrate the device. The

CAL pin must be strobed high for a minimum of

4 clock cycles. The falling edge will initiate a

calibration cycle. A simple power-on reset circuit

can be built using a resistor and capacitor (see

Figure 16). The resistor and capacitor values

should allow for clock or oscillator startup time,

and the voltage reference stabilization time.

+5V

C

R

CS5501

CAL

SC2

SC1

Figure 16. Power-On Reset Circuitry

(Self-Calibration Only)

Due to the devices’ low power dissipation and

low temperature drift, no warm-up time is re-

quired to accommodate any self-heating effects.

Sleep Mode

The CS5501/CS5503 include a sleep mode

(SLEEP = DGND) which shuts down the internal

analog and digital circuitry reducing power con-

sumption to less than 10 µW. All calibration

coefficients are retained in memory such that no

time is required after "awakening" for recalibra-

tion. Still, the CS5501/CS5503 will require time

for the digital filter to settle before an accurate

DS31F2

reading will occur after a rising edge on SLEEP

occurs.

Battery Backed-Up Calibrations

The CS5501/CS5503 use SRAM to store calibra-

tion information. The contents of the SRAM will

be lost whenever power is removed from the chip.

Figure 17 shows a battery back-up scheme that

can be used to retain the calibration memory dur-

ing system down time and/or protect it against

intermittent power loss. Note that upon loss of

power, the SLEEP input goes low, reducing

power consumption to just 10 µW. Lithium cells

of 3.6 V are available which average 1750 mA-

hours before they drop below the typical 2 V

memory-retention specification of the

CS5501/CS5503.

1N4148

10 Ω

+5V

47kΩ

0.1 µF

Vd

14

15

1N4148

VA+

VD+

Vb

1N4148

CS5501

8

5

CS5503

AGND

DGND

11

SLEEP

(2V+Vd) < Vb < 4.5V

VA-

7

VD-

6

0.1 µF

-5V

0.1 µF

10 Ω

0.1 µF

Figure 17. Example Calibration Memory Battery

Back-Up Circuit

When SLEEP is active (SLEEP = DGND), both

VD+ and VA+ must remain powered to no less

than 2 V to retain calibration memory. The VD-

and VA- voltages can be reduced to 0 V but must

not be allowed to go above ground potential. The

negative supply must exhibit low source imped-

ance in the powered-down state as the current into

the VA+ pin flows out the VA- pin. (AGND is

only a reference node. No power supply current

flows in or out of AGND.) Care should be taken

27

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