
STM8AF61xx, STM8AF62xx
Figure 39. SPI timing diagram - master mode
(IGH
.33 INPUT
#0(!
#0/,
#0(!
#0/,
TC3#+
#0(!
#0/,
#0(!
#0/,
-)3/
).0 54
TSU-)
-/3)
/545 4
TW3#+(
TW3#+,
-3 ").
TH-)
- 3" /54
TV-/
") 4 ).
" ) 4 /54
TH-/
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
Electrical characteristics
TR3#+
TF3#+
,3" ).
,3" /54
AI
Doc ID 14952 Rev 6
67/89