Electrical characteristics
STM8AF61xx, STM8AF62xx
Figure 34. Typical NRST pull-up resistance RPU vs VDD
60
55
50
-40°C
25°C
85°C
125°C
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 35. Typical NRST pull-up current Ipu vs VDD
140
120
100
80
60
-40°C
25°C
40
85°C
20
125°C
0
0
1
2
3
4
5
6
VDD [V]
The reset network shown in Figure 36 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 38:
NRST pin characteristics), otherwise the reset is not taken into account internally.
Figure 36. Recommended reset pin protection
VDD
STM8A
External
reset
circuit
(optional)
0.1µF
NRST
RPU
Filter
Internal reset
64/89
Doc ID 14952 Rev 6