RTL8111C
Datasheet
Figure 27. Reference Clock System Measurement Point and Loading
8.8.4. Auxiliary Signal Timing Parameters
Symbol
TPVPERL
TPERST-CLK
TPERST
TFAIL
TWKRF
Table 36. Auxiliary Signal Timing Parameters
Parameter
Min
Max
Units
Power Stable to PERSTB Inactive
100
-
ms
REFCLK Stable before PERSTB Inactive
100
-
µs
PERSTB Active Time
100
-
µs
Power Level Invalid to PWRGD Inactive
-
500
ns
LANWAKEB Rise – Fall Time
-
100
ns
3.3 Vaux
3.3/12V
PERSTB
REFCLK
PCI-E Link Inactive
Power Stable
Wakeup Event
Clock Stable
Clock not
Stable
T PVPERL
T PERST-CLK
Active
Inactive
TPERST
T FAIL
Figure 28. Auxiliary Signal Timing
Power Stable
Clock Stable
Active
Integrated Gigabit Ethernet Controller for PCI Express
39
Track ID: JATR-1076-21 Rev. 1.5