dsPIC30F2011/2012/3012/3013
FIGURE 1-2:
dsPIC30F2012 BLOCK DIAGRAM
Interrupt
Controller
24
Address Latch
Program Memory
(12 Kbytes)
Data Latch
Y Data Bus
PSV & Table
Data Access
24 Control Block
8
16
24
PCU PCH PCL
Program Counter
Stack
Control
Logic
Loop
Control
Logic
X Data Bus
16 16
16
16
Data Latch Data Latch
Y Data
RAM
(512 bytes)
Address
Latch
X Data
RAM
(512 bytes)
Address 16
Latch
16 16
16
Y AGU
X RAGU
X WAGU
16
ROM Latch
24
Effective Address
16
PORTB
16
Instruction
Decode &
Control
IR
Decode
16
16 x 16
W Reg Array
16 16
PORTC
OSC1/CLKI
Timing
Generation
MCLR
VDD, VSS
AVDD, AVSS
Power-up
Timer
Oscillator
Start-up Timer
POR/BOR
Reset
Watchdog
Timer
Low-Voltage
Detect
DSP
Engine
Divide
Unit
ALU<16>
16
16
PORTD
12-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C™
Timers
SPI1
UART1
PORTF
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
AN6/OCFA/RB6
EMUD2/AN7/RB7
AN8/OC1/RB8
AN9/OC2/RB9
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
OSC2/CLKO/RC15
EMUC2/IC1/INT1/RD8
IC2/INT2/RD9
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
CN17/RF4
CN18/RF5
SCK1/INT0/RF6
© 2008 Microchip Technology Inc.
DS70139F-page 13