datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

R5F10367DSP-X0 View Datasheet(PDF) - Renesas Electronics

Part Name
Description
MFG CO.
R5F10367DSP-X0 Datasheet PDF : 110 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
RL78/G12
2. ELECTRICAL SPECIFICATIONS (A, D: TA = 40 to +85°C)
<R> (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = 40 to +85°C, 1.8 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed main) Unit
Mode
MIN.
MAX.
MIN.
MAX.
SCKp cycle time
tKCY1
tKCY1 4/fCLK 2.7 V VDD 5.5 V
167
500
ns
2.4 V VDD 5.5 V
250
500
ns
1.8 V VDD 5.5 V
500
ns
SCKp high-/low-level width tKH1,
tKL1
4.0 V VDD 5.5 V
2.7 V VDD 5.5 V
tKCY1/212
tKCY1/250
ns
tKCY1/218
tKCY1/250
ns
2.4 V VDD 5.5 V
tKCY1/238
tKCY1/250
ns
1.8 V VDD 5.5 V
tKCY1/250
ns
SIp setup time (to SCKp)
tSIK1
Note 1
4.0 V VDD 5.5 V
2.7 V VDD 5.5 V
44
110
ns
44
110
ns
2.4 V VDD 5.5 V
75
110
ns
SIp hold time
(from SCKp) Note 2
Delay time from SCKpto
SOp output Note 3
tKSI1
tKSO1
1.8 V VDD 5.5 V
C = 30 pF Note4
110
ns
19
19
ns
25
25
ns
Notes 1.
2.
3.
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is
only for the R5F102 products)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is only for the
R5F102 products.))
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 33 of 106

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]