CS42L56 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS42L56

Ultralow Power, Stereo Codec with Class H Headphone Amp

Cirrus Logic 

4.5.1

CS42L56

Power Control Options

The method by which the CS42L56 decides which set of rail voltages is supplied to the amplifier output

stages depends on the settings of the Adaptive Power bits (ADPTPWR) found in “Class H Control (Ad-

dress 08h)” section on page 63. As detailed in this section, there are four possible settings for these bits:

standard Class AB mode (settings 01 and 10), adapt to volume mode (setting 00) and adapt to signal (set-

ting 11).

Referenced Control Register Location

ADPTPWR[1:0] ................... “Adaptive Power Adjustment” on page 63

4.5.1.1 Standard Class AB Mode (setting 01 and 10)

When the Adaptive Power bits are set to either 01 or 10, the rail voltages supplied to the amplifiers will be

held to ±VCP/2 or ±VCP, respectively. For these two settings, the rail voltages supplied to the output stag-

es are held constant, regardless of the signal level, internal volume settings, or the settings of the AIN and

DIN advisory volume registers. In either of these two settings, the amplifiers in the CS42L56 simply oper-

ate in a traditional Class AB configuration.

4.5.1.2 Adapt to Volume Mode (setting 00)

When the Adaptive Power bits are set to 00, the Class H controller decides which set of rail voltages to

send to the amplifiers based upon the gain and attenuation levels of all active internal processing blocks.

The active processing blocks are determined by the signal path configured; the configured path then dic-

tates which volume settings affect the controller. The paths available in the CS42L56 are (1) analog-in to

analog-out, (2) analog-in/digital-mix to analog-out and (3) digital-in to analog out.

AINADV [7 :0]

0 to -102dB

MICxBOOST

+10 or +20dB

PDNMICx

PGAAVOL [5:0]

PGAB =A

+12 to -6dB

PGA

1

ADCxMUX[ 1:0]

PDN_ADCx

ADCB=A

DIGSUM[1:0]

BOOSTx

0 or +20dB

ADC

ADCxMUTE

ADCxATT[7 :0 ]

0 to -96dB

AMIXxMUTE

AMIXxVOL [6:0]

+12 to -51.5dB

2

ADCxSWAP[1:0]

Mix/

Swap

HPxMUX

HPxVOL [6:0]

HPxMUTE

PDN_HPx[1:0]

HPDETECT (pin)

+12 to -60dB

HP

3

0 to -102dB

DINADV[7 :0]

PMIXxMUTE

PMIXxVOL [ 6:0 ]

+12 to -51.5dB

PMIXxSW AP [1 :0]

Mix/

Swap

BEEP [ 1:0 ]

Beep

Generator

BPVOL [4:0]

+6 to -50dB

BASS [3 :0]

TREB[3:0]

+12 to -10.5dB

Bass/Treble

Boost/Cut

TCEN

PDN_DSP

MSTxMUTE

MSTxVOL[7:0]

+12 to -102 dB

PLYBCKB =A

DAC

LINE

LINExMUX

+12 to -60dB

LINExVOL [6:0]

LINExMUTE

PDN_ LINx[ 1:0 ]

HPDETECT (pin)

Non-volume controls (italicized ) affect how the Class H

controller interprets the various volume settings.

Figure 21. Class H Volume-Adapt Paths

Certain controls for the processing blocks in the signal path (such as B=A, mux, swap, mix and various

enables) do not directly affect the controller’s total volume sum. These controls do, however, have an in-

direct effect since they determine how the volume setting of the relevant processing block contributes to

the controller’s sum. These controls (italicized in Figure 21) determine whether or not the associated vol-

DS851F2

39

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