CS42L56 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS42L56 Datasheet PDF : 92 Pages
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CS42L56
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = GND = AGND, Logic 1 = VL, LRCK, SCLK, SDOUT CLOAD = 15 pF.
Parameters
Symbol
Min
Max Units
RESET pin Low Pulse Width
(Note 20)
1
-
MCLK Frequency
(See “Serial Port Clocking”
on page 47)
MCLK Duty Cycle
45
55
Slave Mode (Figure 8)
Input Sample Rate (LRCK)
Fs
(See “Serial Port Clocking”
on page 47)
LRCK Duty Cycle
45
55
SCLK Frequency
SCLK Duty Cycle
1/tPs
-
45
68•Fs
55
LRCK Setup Time Before SCLK Rising Edge
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode (Figure 9)
tss(LK-SK)
40
-
tss(SDO-SK)
20
-
ths(SK-SDO)
30
-
tss(SD-SK)
20
-
ths
20
-
Output Sample Rate (LRCK)
Fs
(See “Serial Port Clocking”
on page 47)
LRCK Duty Cycle
45
55
SCLK Frequency
SCLK Duty Cycle
SCLK = MCLK mode
All Other Modes
RATIO[4:0] = ‘xxx00’ or ‘xxx11’
1/tPm
1/tPm
-
12.0000
-
68•Fs
45
55
RATIO[4:0] = ‘xxx01’ (Note 21)
33
66
LRCK Time Before SCLK Falling Edge
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
tsm(LK-SK)
-
±2
tsm(SDO-SK)
20
-
thm(SK-SDO)
30
-
tsm(SD-SK)
20
-
thm
20
-
ms
MHz
%
kHz
%
Hz
%
ns
ns
ns
ns
ns
Hz
%
MHz
Hz
%
%
ns
ns
ns
ns
ns
Notes:
20. After powering up the CS42L56, RESET should be held low after the power supplies and clocks are
settled. This specification is valid with the recommended capacitor on VDFILT.
21. When the RATIO[1:0] = ‘01’, the device will periodically extend the SCLK high time to compensate for
the resulting fractional MCLK/SCLK ratio.
LRCK
tss(LK-SK)
//
//
tP
SCLK
//
//
//
//
SDOUT
tss(SDO-SK)
//
//
ths(SK-SDO)
//
MSB
//
SDIN
//
tss(SD-SK)
//
ths
MSB
Figure 8. Serial Port Timing (Slave Mode)
LRCK
SCLK
//
tsm(LK-SK)
//
//
// tPm
//
//
//
//
SDOUT
tsm(SDO-SK)
//
//
thm(SK-SDO)
//
MSB
//
SDIN
//
tsm(SD-SK)
//
thm
MSB
Figure 9. Serial Port Timing (Master Mode)
22
DS851F2
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