TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED)
SFR Name
SFR
Addr
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6 Bit 5
XBREV
DISICNT
BSRAM
SSRAM
Legend:
0050
BREN
XB<14:0>
0052
—
—
Disable Interrupts Counter Register
0750
—
—
—
—
—
—
—
—
—
—
—
0752
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 4
—
—
Bit 3
—
—
Bit 2
Bit 1
Bit 0
IW_BSR IR_BSR RL_BSR
IW_SSR IR_SSR RL_SSR
All
Resets
xxxx
xxxx
0000
0000