LFE3-17EA-7FN672I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
MFG CO.
LFE3-17EA-7FN672I Datasheet PDF : 140 Pages
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Architecture
LatticeECP3 Family Data Sheet
MULTADDSUBSUM DSP Element
In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands BA and BB of Slice 0. Additionally, the operands AA and AB are multiplied and the
result is added/subtracted with the result of the multiplier operation of operands BA and BB of Slice 1. The results
of both addition/subtractions are added by the second ALU following the slice cascade path. The user can enable
the input, output and pipeline registers. Figure 2-30 and Figure 2-31 show the MULTADDSUBSUM sysDSP ele-
ment.
Figure 2-30. MULTADDSUBSUM Slice 0
From FPGA Core
C
SRIB
SRIA
I
AA
IR
AB
IR
MULTA
OPCODE
IR
BA
IR
MULTB
BB
SROB
IR
IR SROA
Previous
DSP Slice
C_ALU
CIN
A_ALU
Rounding
0
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
PR A_ALU
0
AMUX
PR
PR
B_ALU
0
BMUX
R= A ± B ± C
R = Logic (B, C)
ALU
==
OR
OR
FR
OR
To FPGA Core
Next
DSP Slice
COUT
2-28
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