STM32F100R4H7BTR(2010) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STM32F100R4H7BTR
(Rev.:2010)

Low & medium-density value line, advanced ARM-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

STMicroelectronics 

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

5.3.13

Figure 25. I/O AC characteristics definition

90%

50%

10%

10%

50%

90%

EXT ERNAL

O UTP UT

ON 50pF

tr(I O)out

tr(I O)out

T

Maximum fr equency is achieved if (tr + tf) 2/3) T and if the duty cycle is (45-55%)

when loaded by 50pF

ai14131

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, RPU (see Table 33).

Unless otherwise specified, the parameters given in Table 36 are derived from tests

performed under the ambient temperature and VDD supply voltage conditions summarized

in Table 8.

Table 36. NRST pin characteristics

Symbol

Parameter

Conditions Min Typ

Max Unit

VIL(NRST)(1) NRST Input low level voltage

VIH(NRST)(1) NRST Input high level voltage

–0.5

2

0.8

V

VDD+0.5

Vhys(NRST)

NRST Schmitt trigger voltage

hysteresis

200

mV

RPU

Weak pull-up equivalent resistor(2) VIN VSS

30

40

VF(NRST)(1) NRST Input filtered pulse

VNF(NRST)(1) NRST Input not filtered pulse

300

50

k

100

ns

ns

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

. the series resistance must be minimum (~10% order)

Figure 26. Recommended NRST pin protection

%XTERNAL

RESETCIRCUIT

6$$

.234

205

—&

)NTERNALRESET

&ILTER

34-&X

AID

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 36. Otherwise the reset will not be taken into account by the device.

Doc ID 16455 Rev 2

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