V350EPC View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
V350EPC Datasheet PDF : 18 Pages
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V350EPC
Table 15: Local Bus Timing Parameters for Vcc = 3.3 Volts +/- 5%
33MHz
# Symbol
Description
Notes Min Max Units
1 TC LCLK period
30
ns
2 TCH LCLK high time
1
12
ns
3 TCL LCLK low time
1
12
ns
4 TSU Synchronous input setup
2
8
ns
4a TSU Synchronous input setup (BLAST)
9
ns
4b TSU Synchronous input setup (W/R, BTERM)
7
ns
4c TSU Synchronous input setup (ADS/AS)
8
ns
4d
TSU
Synchronous input setup (address, data,
byte enables)
7
ns
4e
TSU
Synchronous input setup for read data
when in local bus master mode
5
ns
5 TH Synchronous input hold
6 TCOV LCLK to output valid delay
3
6a
TCOV
LCLK to output valid delay (address, data,
byte enable, parity)
3 ns
4 14 ns
4 16 ns
7 TCZO LCLK to output driving delay
8 TCOZ LCLK to high impedance delay
9 TRST Reset period when LRST used as input
4 16 ns
4
4 16 ns
16·TC
ns
Notes:
1. Measured at 1.5V.
2. All local bus signals except those in 4a, 4b, 4c, 4d and 4e.
3. All local bus signals except those in 6a.
4. READY, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Table 16: PCI Bus Timing Parameters for Vcc = 5 or 3.3 Volts +/- 5%
# Symbol
Description
1
TC PCLK period
2
TSU Synchronous input setup to PCLK
2a TSU Synchronous input setup to PCLK (GNT)
Notes
1
Min Max Units
30
ns
7
ns
10
ns
16
V350EPC Data Sheet Rev 1.1
Copyright © 1998, V3 Semiconductor Inc.
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