V292PBC-40REVB2 View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

V292PBC-40REVB2

LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V292PBC

Table 14: PCI Bus Timing Parameters for Vcc = 5 Volts +/- 5%

4 TCOV PCLK to output valid delay

4a TCOV PCLK to output valid delay (REQ)

5 TCZO PCLK to output driving delay

6 TCOZ PCLK to high impedance delay

7 TRST Reset period when PRST used as input

Notes:

1. All PCI bus signals except those in 2a.

2. All PCI bus signals except those in 4a.

2

3

11 ns

4

12 ns

4

11 ns

5

18 ns

16·TC

4.3 Serial EEPROM Port TImings

The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms

generated are shown in Figure 4.

Figure 4: Serial EEPROM Waveforms and Timings

START CONDITION

512 PCI BUS

CLOCKS

STOP CONDITION

SCL

SDA

256 PCI BUS

CLOCKS

256 PCI BUS

CLOCKS

5.0 Revision History

Table 15: Revision History

Revision

Number

Date

Comments and Changes

2.4

5/98 Data sheets update to B2-step values

2.3

10/96

Data Book revision.

1. In Table 3, changed “LPAR[3:0]” to “LPAR[3:0]”.

14

V292PBC Data Sheet Rev 2.4

Copyright © 1998, V3 Semiconductor Inc.

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