ACS8515REV2.1 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8515REV2.1 Datasheet PDF : 50 Pages
| |||
ADVANCED COMMUNICATIONS
Register Map Description
ACS8515 Rev2.1 LC/P
FINAL
Table 11. Register Map Description
Addr. Parameter Name
(Hex)
02 chip_revision
cnfg_control1
03
04 cnfg_control2
sts_interrupts
Description
This read-only register contains the chip revision number
This revision = 1
Last revision (engineering samples) = 0
Bits (7:6) Unused
Default
Value (bin)
00000001
Bit 5
=1 32/24MHz to APLL: Feeds 2x Dig2 frequency to the APLL instead of the normal 77.76Mhz.
Thus the normal OC3/STM1 outputs are replaced with multiple E1/T1 rates. Note: Dig2 set bits
(Reg. 39h Bits (7:6)) must be set to 11 for this mode.
=0 77.76MHz to APLL
Bit 4
=1 Synchronizes the dividers in the output APLL section to the dividers in the DPLL section
such that their phases align. This is necessary in order to have phase alignment between inputs
and output clocks at OC3 derived rates (6.48 MHz to 77.76 MHz). Keeping this bit high may be
necessary to avoid the dividers getting out of synchronization when quick changes in frequency
occur such as a force into Free-Run.
=0 The dividers may get out of phase following step changes in frequency, but in this mode the
correct number of high frequency edges is guarenteed within any synchronization period. The
output will frequency lock (default).
The device will always remain in synchronization 2 seconds from a reset, before the default
setting applies.
XX000000
Bits 3
Test control - leave unchanged, or set to '0'
Bit 2
=1 When in 8k locking mode the system will lock to the rising input clock edge.
=0 When in 8k locking mode the system will lock to the falling input clock edge.
Bits (1:0) Test controls - leave unchanged, or set to '00'
Bits (7:6) Unused.
XX100010
Bits (5:3) define the phase loss flag limit. By default set to 4 (100) which corresponds to
approximately 140°. A lower value sets a corresponding lower phase limit. The flag limit
determines the value at which the DPLL indicates phase lost as a result of input jitter, a phase
jump, or a frequency jump on the input.
Bits (2:0) Test controls - leave unchanged or set to '010'.
This register contains one bit for each bit of sts_sources_valid, one for loss of reference the
device was locked to, and another for the operating mode. All bits are active high.
All bits except the 'main ref failed' bit (bit 14) are set on a 'change' in the state of the relevent
status bit, i.e. if a source becomes valid, or goes invalid it will trigger an interrupt. If the
Operating Mode (register 9) changes state the interrupt will be generated.
Bit 14 (main ref failed) of the interrupt status register is used to flag inactivity on the reference
that the device is locked to much more quickly than the activity monitors can support. If bit 6 of
the cnfg_monitors register (register 48) (flag ref loss on TDO) is set, then the state of this bit is
driven onto the TDO pin of the device.
All bits are maskable by the bits in the cnfg_interrupt_mask register. Each bit may be cleared
individually by writing a '1' to that bit, thus resetting the interrupt. Any number of bits can be
cleared with a single write operation. Writing '0's will have no effect.
Revision 2.01/December 2005 Semtech Corp.
21
www.semtech.com
Share Link: 