LFSC3GA80E-7FN256C View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

MFG CO.

LFSC3GA80E-7FN256C

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Figure 2-22. Output Register Block1

Architecture

LatticeSC/M Family Data Sheet

SDR

Register

To

Tri-state

Block

From

Routing

OPOS0

ONEG0

OPOS1

ONEG1

From

Control

MUX

LCLKOUT

HCLKOUT

DDR/Shift Register Block

• DDR

• DDR + half clock

• DDR + shift x2

• DDR + shift x42

• Shift x2

• Shift x42

DO

(to PURESPEED

I/O Buffer)

Notes:

1. CE, Update, Set and Reset not shown for clarity.

2. By four shift modes utilizes DDR/Shift register block from paired PIO.

3. DDR/Shift register block shared with tristate block.

Figure 2-23. Output/Tristate DDR/Shift Register Block

OPOS0

(Can act as OPOS2

when paired)

Bypass Used for

DDR/DDRX Modes

From paired PIO

( x4 shift modes)

To paired PIO

(x4 shift modes)

Shift x2 / x4

Output

OPOS1

(Can act as OPOS3

when paired)

LCLKOUT

HCLKOUT

POS Update

NEG Update

ONEG0

(Can act as ONEG2

when paired)

Bypass Used for

DDR/DDRX Modes

From paired PIO

( x4 shift modes)

To paired PIO

(x4 shift modes)

TSDDR/DDRX

ODDR/DDR/

X2/X4

ONEG1

(Can act as ONEG3

when paired)

2-21

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