
ST7LITE3xF2
SERIAL PERIPHERAL INTERFACE (SPI) (cont’d)
Figure 48. Serial Peripheral Interface Block Diagram
MOSI
MISO
SCK
SPIDR
Data/Address Bus
Read
Read Buffer
Interrupt
request
8-bit Shift Register
SOD
bit
Write
7
SPIF WCOL OVR MODF 0
SPICSR 0
SOD SSM SSI
SPI
STATE
CONTROL
SS 1
0
MASTER
CONTROL
7
SPICR 0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
SERIAL CLOCK
GENERATOR
SS
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